When RTL design is correct, we need a logic design in our targeted logic family.
The design partitions naturally into the datapath (80%), and the control (20%).
Use tools to translate an RTL description in verilog or VHDL into logic on the targeted family. Synthesis engines have got more sophisticated over the years and usually can optimise for speed or area. Synthesis will do better than an inexperienced designer, but an experienced designer would hope to do about 10% better.
Design and optimise the logic from one bit of the system, then replicate for an n-bit word. There is a lot of regularity in the datapath, which saves a lot of effort.
There are a number of approaches to implementing the logic:
Ad-hoc logic will usually give the best performance and the smallest area but takes the most design effort and is harder to change.
Multiplexers, ROMs and PLAs are a more structured way of designing logic, but have performance and area penalties.
A 2->1 multiplexer can implement any function of two variables with one applied to the select input and the other applied to data inputs.
ROM uses inputs as an address and its contents store the desired operation.
Programmable Logic Array (PLA) has a 2D array of transistors in an AND plane, forming product (and) terms. After buffering, the and terms are ORed together in a 2D transistor array in the OR plane.
The size of the AND plane is the number of inputs x the number of AND terms. The size of the OR plane is the number of AND terms x number of outputs.
Any Boolean function can be expressed as a sum (OR) of products (AND).
PLAs are larger than ad-hoc logic and are slower because of buffering required and the length of the lines which run the length of the 2D array.
Designing one datapath is called a bit-slice approach.
This is a good way to deal with control, because it is very irregular when compared to the datapath. We get an efficient design from the synthesis engine because you have to write explicit code for the RTL of each signal.
The more structured approach of a PLA is recomended for the combinatorial logic of the control. Adding an input and output register, the control forms a finite state machine. This structure brings regularity to irregular functions. In the PLA, we have a transistor at every node, and we only have to decide whether to connect transistor to product or sum line.
Somme outputs from the output register are fed back int the input register and these are current state bits. Logic in the PLA then determines the next state.
The only disadvantage is more area, longer line lengths, nore buffering on inputs to each plane, so it’s slower than ad-hoc.