Requirements analysis

Design choices

ASIC

Application Specific Integrated Circuit

Full custom

• Design your own logic & flip flop cells (or whatever). These have to be designed from scratch and laid out.

Advantages

• Total flexibility
• Best performance, power and area.
• Easier to protect IP

Disadvantages

• Very long development times
• Very high (initial) production costs (need full mask etc). Only for high volume production.

Semi-custom

• Uses predefined, characterized & laid out cells of functions which the manufacturer has optimised.
• Cells normally butt together with power & ground in standard positions. Just add routing (tm).

Advantages

• Much easier - reduced design time. (still quite long though).
• Less chance of errors.
• Not as good for area, power & performance as full custom (usually acceptable).
• Usually fairly easy to protect IP (though not as much as Full custom.

Disadvantages

• Not quite as flexible as full custom.
• Aspensive to rework (like full custom).
• High production costs (like full custom).
• Fairly high volume product (not as much as full custom).

Programmable Logic Devices (PLDs)

Program device to provide a specific function. These devices have a 2D array of identical logic cells. Sometimes ‘mode bits’ specify how these are internally connected. Signal routing through the cells is through a ‘switch box’ approach, with the routing pattern and mode bits held in reprogrammable RAM.

Advantages

• Excellent for prototyping - virtually no cost to iterate.
• Fast development time.
• Easy to change.
• Fairly low design costs.
• Reasonable speed and complexity.
• Decreased time to finished product.

Disadvantages

• Limited flexibility.
• Cony appropriate for low volume product.
• Worst for area, speed and performance.
• Difficult to protect IP, and easy to copy.

Nowadays, the usual approach is to combine standard cells with externally provided IP blocks (an ARM for example). FPGAs can be used to prototype large sections of a design. It is uncommon to design at the gate level, rather the behaviour is described with a HDL, then use CAD tools to translate (synthesize) this to logic on a target.

Actual Requirements analysis

These are obtained by talking to the end user. In the lab we want to design a simple RISC, general purpose processor at the RTL level and test it.

Reasons for RISC

• Simple datapath – load-store architecture, so it only requires a register bank, and an ALU.

• Only three types of instructions:

  Register to register

  • Read operands from register bank, do operations in the ALU, and write results to the reg bank.

  Load/Store operations

  • Load reg from memory or store reg to memory.
  • Use execute unit to form addresses.

  Branch instructions

  • Add an offset to the value of PC, and if some condition is satisfied, write to the PC.
  • Get new instruction stream from here.
  • Normally, PC is in the register bank.

• RISC has simpler control because there are relatively few addressing and instruction modes. Function bits have a specific meaning. Decoding is simple and quick. As a result, instruction decoding, operand reading and any arithmetic can be done in one step (clock period). This means that the instructions take 3 phases to be performed:

  • Fetch
  • Execute
  • Writeback

  One instruction therefore takes 3 cycles - less than CISC.

  The control of a RISC machine is normally simple enough to be hardwired, unlike CISC, where microcode is normally used.