The top level specification - the hand-waving stops here. This is a precise definition of what the system does, from the perspective of a programmer of the system.
For a processor, the system spec is the instruction set.
See chapter 5 for instruction set of STUMP.
The choice of a 16-bit word and the usual 3-address RISC instruction format means that the number of registers in our register bank is restricted to 8, and there can be only 8 different instructions.
See lab manual.
From our instruction definition, we want to generate a top level behavioural model in some language which precisely describes the effect of instructions.
We will use Verilog because:
The model needs to incorporate some features of the hardware (eg. registers, ALU, shifter etc.) because these are specified by the instructions.
One way of moving towards writing a behavioural model is to produce a flow diagram of the sequence of actions required by instructions. The Verilog model is then written from the flow diagrams.
The verilog code is a single allways loop, which preceeds from fetch to execute to writeback, then repeats. Note that there is no clock.
Once we have a model, it needs to be tested. We do that by driving the inputs, and monitoring the outputs. In genreal, we can’t do exhaustive tests, but we need to devise tests which are thorough enough to give us confidence that the design is correct. These tesp programs are used at every level of the hierachy, and on the manufactured device.
The most common way of testing is to use a test bench. The test bench consists of the device-under-test, and a tester. The tester is usually a verilog model. For the stump processor, the tester is a memory, holding instructions and any data.
Finally, do a sanity-check on the number of pins required on chip.