When the architectural design is correct, move down to the Register Transfer Level.
This level describes the datapath as an internal behavioural description. This consists of registers and combinatorial logic blocks.
Designs contain flip-flops (not sandals), so have a clock.
One of the best ways of arriving at the datapath design is to draw the hardware for each phase (fetch, execute, writeback), then combine the diagrams – a divide and conquer approach.