Verilog

• Hardware Description Language.
• Designed in mid-eighties.
• Widely used in industry.

We can describe hardware at 3 levels:

External Behavioural View

For describing algorithms, or the system spec. This can’t be translated to real hardware.

Internal behavioural view

RTL (registers and combinatorial logic blocks).

Structural

Gates (bad move).

We can mix verilog levels within a design, so we can start off the design with a set of high-level, external behavioural modules, and gradually replace them with more detailed modells as design progresses, and can run the same simulation programs on the evolving design.

One example th this is the STUMP test bench. These top-level components are connected by a schematicL - memory (external model in verilog. This has verilog system calls to load and dump memory.) - datapath (schematic generates verilog) - Control (internal behavioural verilog)

correction:

page 14, cross out REG_BANK=... page 7, append “we can’t access an individualbit in array.”